IIT Madras will host the 3rd Digital India RISC‑V (DIR‑V) Symposium on 1–2 August 2026 at the IIT Madras Research Park, organised by MeitY and RISC‑V International.
RISC‑V: Technical Profile
- Definition: Open standard instruction set architecture developed at University of California, Berkeley.
- Architecture type: Reduced Instruction Set Computer (RISC); modular base ISA with optional extensions.
- Base ISAs: RV32I and RV64I (integer bases).
- Key extensions: M (multiply/divide), A (atomics), F (single‑precision FP), D (double‑precision FP), C (compressed).
- Toolchain support: GCC and LLVM backends; simulators include Spike and QEMU ports.
India’s Open‑Source Chip Push
- DIR‑V Initiative: Platform for industry‑academia collaboration, developer engagement and a Grand Challenge hackathon.
- MeitY role: Nodal ministry for electronics, information technology and digital governance; promoter of semiconductor and design initiatives.
- Design emphasis: Custom SoCs for IoT, edge AI, secure computing and trusted platforms.
Strategic & Exam Facts
- Event facts: 3rd DIR‑V Symposium, 1–2 Aug 2026; registration deadline 28 Jul 2026; venue IIT Madras Research Park, Chennai.
- Standards body: RISC‑V International maintains ISA specifications and extension governance.
- Policy linkage: Open‑ISA adoption enables domestic chip design capabilities and reduces dependence on proprietary ISAs.
IASPOINT Booster Facts
- Licensing: RISC‑V specifications are publicly available and intended to be royalty‑free to implement.
- Primary use cases: Microcontrollers, embedded systems, research processors and edge devices.