Modified Programme for Semiconductors

The Modified Programme for Development of Semiconductors and Display Manufacturing Ecosystem in India is a critical Central Sector Scheme under the Ministry of Electronics and Information Technology (MeitY). Launched to establish a sustainable, trusted, and globally competitive semiconductor and display ecosystem, this program seeks to secure India’s digital sovereignty and integrate its domestic manufacturers into the global electronics value chain. The initial strategy launched in December 2021 as India Semiconductor Mission (ISM) 1.0 carried an overall incentive framework of ₹76,000 crore (over $10 billion USD). To match shifting global technology configurations and intense competition, the Union Cabinet updated the policy into the “Modified Programme” to offer uniform, flat-rate fiscal incentives. The Union Budget 2026–27 expanded this strategy by introducing the India Semiconductor Mission (ISM) 2.0 with an allocation of ₹1,000 crore specifically targeting downstream supply chains, specialized raw materials, and indigenous Intellectual Property (IP) development. For the financial year 2026–27, the Modified Programme under ISM features an overall direct financial outlay of ₹8,000 crore.

Core Financial Configurations and Uniform Fiscal Support

The most significant policy pivot from the original scheme to the Modified Programme is the harmonization of central fiscal incentives across all major manufacturing sub-sectors.

The 50% Pari-Passu Mechanism

• Under the modified guidelines, the Central Government provides uniform financial support covering 50% of the project cost or capital expenditure (CAPEX) on a pari-passu basis.
• Pari-passu financing ensures that the government releases its fiscal support concurrently and in equal proportion alongside the equity or capital deployed by the private investor or consortium, reducing front-end liquidity stress.
• This flat 50% subsidy replaces older, tiered incentive structures that previously offered lower support (ranging from 30% to 40%) depending on the node size or specific facility type.

State Government Subsidies and Dedicated Policies

• To complement MeitY’s central fiscal push, various state governments offer additional capital subsidies ranging from 20% to 35% on CAPEX, alongside subsidized land, specialized logistics corridors, and high-purity water supply.

Sub-Schemes and Operational Pillars of the Programme

The umbrella Modified Programme is executed via four highly technical sub-schemes tailored to specific layers of the microelectronics manufacturing and design value chain.

1. Modified Scheme for Setting Up of Semiconductor Fabs

• Target: Establishment of large-scale commercial Silicon Semiconductor Fabrication units (Fabs).
• Fiscal Incentive: 50% of the overall project cost on a pari-passu basis.
• Operational Goal: Attracting massive global and domestic consortia to construct greenfield fabrication facilities for processing silicon wafers, targeting high-volume technology nodes used in power electronics, automotive components, and consumer appliances.

2. Modified Scheme for Setting Up of Display Fabs

• Target: Large-scale manufacturing units for advanced displays, including Liquid Crystal Displays (LCDs) and Organic Light Emitting Diodes (OLEDs).
• Fiscal Incentive: 50% of the project cost on a pari-passu basis.
• Strategic Value: Displays represent a significant percentage of the bill-of-materials in smartphones and televisions; domestic display fabs drastically reduce component import dependency.

3. Modified Scheme for Compound Semiconductors, Silicon Photonics, Sensors, and ATMP/OSAT Facilities

• Target: Specialized niche facilities including Compound Semiconductors (e.g., Gallium Nitride, Silicon Carbide), Silicon Photonics, Micro-Electromechanical Systems (MEMS) sensors, Discrete Semiconductors, and Assembly, Testing, Marking, and Packaging (ATMP) / Outsourced Semiconductor Assembly and Test (OSAT) units.
• Fiscal Incentive: 50% of the capital expenditure (CAPEX) on a pari-passu basis.
• Strategic Value: This sub-scheme drives lower-latency, smaller-footprint packaging technologies that are vital for 5G modules, Artificial Intelligence hardware, and aerospace applications.

4. Design Linked Incentive (DLI) Scheme

• Target: Domestic fabless startups, micro, small, and medium enterprises (MSMEs) engaged in semiconductor design for Integrated Circuits (ICs), Chipsets, System-on-Chips (SoCs), and Systems & IP Cores.
• Product Design Linked Incentive: Financial support up to 50% of the eligible expenditure, capped at ₹15 crore per application.
• Product Deployment Linked Incentive: An incentive of 6% to 4% on net sales turnover over five years, capped at ₹30 crore per application, granted to designs deployed in commercial products.
• Ecosystem Support: Provides infrastructure access via the centralized ChipIN Centre hosted at C-DAC Bangalore, which offers cloud-based Electronic Design Automation (EDA) tools, virtual prototyping, and multi-project wafer fabrication access.

Strategic Objectives and Institutional Architecture

India Semiconductor Mission (ISM)

• Established as an autonomous specialized business division within the Digital India Corporation.
• Functioning as the nodal agency, ISM is led by international semiconductor industry experts who manage technical appraisals, project monitoring, and coordination with inter-ministerial committees.
• Implements strategic roadmaps to secure global supply partnerships, manage technology transfers, and protect domestic critical information infrastructure.

Key Objectives of the Mission

• Developing a secure and resilient semiconductor supply chain that includes continuous access to raw materials, specialty chemical formulations, high-purity industrial gases, and advanced manufacturing machinery.
• Advancing research and development collaborations to bridge academic milestones with marketplace manufacturing, scaling nodes progressively from mature structures down to advanced 3-nanometer and 2-nanometer configurations.
• Utilizing demographics to train a specialized, industrial-grade VLSI (Very Large Scale Integration) and embedded system engineering workforce.

Budgetary Outlays and Structural Targets (FY 2026–27)

The fiscal distribution within Demand No. 27 for MeitY establishes clear financial priorities for the execution of the program.

Fiscal Allocations under the Modified Programme (Budget Estimates 2026–27)

• Compound Semiconductors, ATMP, and OSAT Facilities: ₹5,000 crore
• Semiconductor Fabs (Silicon): ₹2,000 crore
• Modernisation of Semi-Conductor Laboratory (SCL), Mohali: ₹900 crore
• Design Linked Incentive (DLI) Scheme: ₹100 crore
• Total Umbrella Modified Programme Allocation: ₹8,000 crore
• India Semiconductor Mission (ISM) 2.0 (New Complementary Outlay): ₹1,000 crore

Target Projections under ISM for FY 2026–27

• Silicon Fabs: Direct deployment of ₹4,000 crore in active annual capital investment, generating direct high-skilled employment for 1,500 professionals.
• Specialized Units (Compound, ATMP, OSAT): Targeted support for 9 distinct manufacturing units, attracting a seasonal investment of ₹11,000 crore.

Strategic Milestones and Allied Academic Programs

Key Operational Achievements

• As of late 2025, 10 major project installations under the ISM framework with a cumulative investment commitment of ₹1.60 lakh crore have been approved across six states.
• Notable sanctioned infrastructure includes an advanced 3D semiconductor packaging unit in Odisha, the Kaynes Semicon plant at Sanand (Gujarat), an integrated compound semiconductor fab facility in Dholera (Gujarat), and a dedicated OSAT facility in Surat (Gujarat).
• The DLI sub-scheme actively fosters 24 domestic semiconductor design startups, which have successfully leveraged their status to attract approximately ₹430 crore in private venture capital funding.

Chips to Startup (C2S) Programme

• Run in tandem with ISM, the C2S scheme acts as the primary human resource driver.
• Targets the creation of 85,000 specialized, industry-ready semiconductor engineers over five years.
• Operationalized across over 100 academic institutions, universities, and research laboratories by providing state-of-the-art EDA tool hardware, designing specialized B.Tech/M.Tech curricula, and funding student-led System-on-Chip (SoC) design projects.

UPSC Prelims Fact File and Exam Trivia

Silicon Fabs vs. Compound Semiconductor Fabs

• Silicon fabs use elemental silicon as the wafer substrate, optimal for traditional, mass-market computing microprocessors.
• Compound semiconductor fabs combine two or more elements from different periodic table groups (e.g., Gallium Nitride – GaN, Silicon Carbide – SiC). These materials feature a wider bandgap, allowing devices to operate at much higher voltages, frequencies, and temperatures, making them foundational for electric vehicle (EV) powertrains and radar systems.

ATMP and OSAT Explained

• ATMP (Assembly, Testing, Marking, and Packaging) and OSAT (Outsourced Semiconductor Assembly and Test) represent the crucial downstream phase of chip production. After raw silicon wafers are printed with circuits at a fab, ATMP/OSAT facilities dice the wafers into individual dies, test their functionality, and enclose them in protective protective casings to enable mounting on circuit boards.

The Semi-Conductor Laboratory (SCL), Mohali

• SCL is an autonomous body under MeitY originally established in 1983. Under the Modified Programme, the government has designated a specific allocation (₹900 crore for FY 2026–27) to legacy-modernize this brownfield facility, shifting its capabilities toward commercial research, prototype fabrication, and developing trusted chips for strategic space and defense sectors.

International Bilateral Alignments

• To fortify its semiconductor value chain against geopolitical shocks, India has signed dedicated Semiconductor Supply Chain Partnership Memorandums of Cooperation (MoCs) with global chip leaders including Japan, the United States, and the European Union (EU).