Semiconductor Fabrication

Semiconductor fabrication, commonly referred to as “semiconductor manufacturing” or “fab operations,” is the highly intricate physical and chemical process of creating integrated circuits (ICs) on thin, crystalline semiconductor sheets called wafers. This phase forms the capital-intensive “foundry” segment of the global electronics supply chain. Because individual circuit details are rendered at the atomic scale, fabrication occurs within hyper-controlled cleanrooms using advanced automated machinery, chemical processing, and photolithography techniques.

Foundries vs. Integrated Device Manufacturers (IDMs)

The commercial business landscape of semiconductor fabrication is structurally divided into two primary operating models:

• The Foundry Model (Pure-Play Foundries): These companies operate strictly as contract manufacturers. They fabricate physical microchips designed by external “fabless” technology entities but do not market chips under their own brand name. Examples include TSMC (Taiwan) and UMC (Taiwan).
• Integrated Device Manufacturers (IDMs): These companies run an vertically integrated model where they design, fabricate, and market their own proprietary microchips inside their own internal wafer fabs. Examples include Intel (USA), Samsung Electronics (South Korea), and Texas Instruments (USA).

The Cleanroom Environment

Fabrication steps are highly vulnerable to microscopic airborne contaminants; a single particle of dust can destroy an entire microchip circuit layout. Fabs operate inside Class 1 or Class 10 cleanrooms.

• Class 1 Cleanrooms: Enforce an environmental threshold where there is no more than one particle of size 0.5 micrometers or larger per cubic foot of air.
• Environmental Controls: Cleanrooms utilize continuous High-Efficiency Particulate Air (HEPA) or Ultra-Low Penetration Air (ULPA) filtration systems, precise laminar airflow, constant humidity controls, and static-dissipative yellow-frequency lighting (to prevent accidental exposure of light-sensitive chemical photoresists).

Core Process Nodes of Wafer Fabrication

The conversion of a polished raw silicon slice into a functioning microchip involves hundreds of sequential processing steps over several weeks, grouped into five core physical operations.

1. Thermal Oxidation and Deposition

• Thermal Oxidation: Exposing silicon wafers to high-temperature oxygen environments (900°C to 1200°C) to grow a highly uniform, protective layer of insulating Silicon Dioxide (SiO₂).
• Thin-Film Deposition: Applying ultra-thin layers of conducting metals (aluminum, tungsten, copper) or insulating materials onto the wafer substrate. This is executed using Chemical Vapor Deposition (CVD), which relies on gas-phase chemical reactions, or Physical Vapor Deposition (PVD), which uses physical sputtering techniques.

2. Photolithography

Photolithography is the central process that prints geometric hardware patterns from a design layout onto the wafer surface.

• Photoresist Application: The wafer is coated with a light-sensitive liquid chemical polymer called a photoresist.
• Exposure: A light source projects the circuit layout patterns through a transparent photomask onto the coated wafer.
• Light Sources and Nodes: Mature nodes utilize Deep Ultraviolet (DUV) light sources (Argon Fluoride lasers at 193nm wavelength). Cutting-edge sub-7nm logic nodes require Extreme Ultraviolet (EUV) lithography equipment, which operates at a highly compressed 13.5nm wavelength to print features at atomic scales.

3. Etching

Etching selectively removes specific regions of deposited thin films or oxides that are not protected by the hardened exposed photoresist layer, leaving behind the desired geometric pathways.

• Wet Etching: Uses liquid chemical acids (such as Hydrofluoric acid) to dissolve materials. It is isotropic (cleaves uniformly in all directions) and used for wider, non-critical process layers.
• Dry Etching (Plasma Etching): Uses high-energy reactive gas plasmas to bombard the wafer surface. It is highly anisotropic (cleaves strictly vertically), enabling the sharp, straight vertical walls required for nanoscale transistors.

4. Ion Implantation and Diffusion (Doping)

To change the electrical conductivity of specific zones on the silicon wafer and form P-type or N-type configurations, the wafer is doped with target impurities.

• Ion Implantation: High-voltage particle accelerators fire high-energy ions of dopant elements (such as Boron, Phosphorus, or Arsenic) directly into the crystalline silicon matrix.
• Thermal Annealing: The wafer is heated to repair structural damage caused by ion bombardment and physically activate the dopant atoms within the silicon lattice.

5. Chemical Mechanical Planarization (CMP)

As multiple metal and insulating layers are stacked onto the wafer, the surface topography becomes uneven. CMP uses an abrasive chemical slurry combined with a rotating polishing pad to grind down and flatten the top wafer surface, ensuring a smooth field for the next photolithography step.

Process Technology Scaling: Mature vs. Advanced Nodes

Fabrication lines are distinguished globally by their minimum process feature sizes, measured in nanometers (nm).

India’s Fabrication Ecosystem and Institutional Framework

India has shifted from structural chip design into full-stack domestic fabrication capabilities under the India Semiconductor Mission (ISM), which provides 50% fiscal capital subsidies for establishing electronics manufacturing plants.

Core Indian Fabrication Projects

• Tata Electronics Dholera Fab (Gujarat): India’s first commercial mega-scale silicon wafer fabrication plant, developed in a joint venture with Powerchip Semiconductor Manufacturing Corporation (PSMC) of Taiwan. Located in the Dholera Special Investment Region, it focuses on mature nodes (28nm and above) to produce microcontrollers, power management chips, and consumer electronics hardware.
• Specialty and Compound Semiconductor Fabs: Several targeted facilities are being set up to support niche technologies. This includes SiCSem (Odisha), which is establishing a production facility for Silicon Carbide (SiC) wide-bandgap semiconductors to supply electric vehicle (EV) powertrains and high-voltage industrial applications.
• Semiconductor Laboratory (SML, Mohali): India’s legacy brownfield brownfield research fabrication facility, which produces specialized space-grade and defense-grade microelectronics at the 180nm node.

Technical Trivia for Prelims

• Ingot Slicing Loss (Kerf Loss): During the initial phase of fabrication, when a single-crystal cylindrical silicon ingot is sliced using diamond wire saws into individual wafers, up to 30% of the ultra-pure silicon is lost as silicon dust (kerf).
• The “Nine Nines” Purity: Electronic-grade silicon (EGS) used in foundries requires a purity level of 99.9999999%. This means that for every one billion silicon atoms, only a single impurity atom is permitted.
• Wafer Size Evolution: Fabs have moved from historical 100mm (4-inch) wafers to the modern global industry standard of 300mm (12-inch) wafers. The larger surface area allows more individual microchip dies to be printed per batch, reducing manufacturing costs.