Semiconductor Nodes

A semiconductor node (also known as a process node or technology node) refers to a specific manufacturing process and design generation for integrated circuits (ICs). Historically, the node name in nanometers (nm) represented the actual physical size of the transistor’s gate length or half-pitch. In contemporary manufacturing, the designation has shifted to a marketing nomenclature that signifies a generation of advancement in transistor density, power efficiency, and processing speed rather than a literal physical measurement.

Evolution of Manufacturing Node Technologies

The architecture of transistors has undergone significant structural transformations to overcome the physical limitations of scaling, such as quantum tunneling and leakage current.

Planar Field-Effect Transistor (Planar MOSFET)

Used down to the 28 nm node, this traditional 2D structure features a flat channel. As dimensions shrank below 28 nm, short-channel effects caused excessive current leakage, rendering further planar scaling unviable for high-performance computing.

Fin Field-Effect Transistor (FinFET)

Introduced commercially at the 22 nm node, FinFET transitioned the transistor into a 3D architecture. The channel is raised into a thin vertical “fin,” and the gate wraps around it on three sides. This design provides superior electrostatic control over the channel, drastically reducing leakage current and enabling scaling down to the 5 nm node.

Gate-All-Around Field-Effect Transistor (GAAFET)

Deployable from 3 nm nodes and below, GAAFET replaces the vertical fin with stacked horizontal nanosheets. The gate completely surrounds the channel on all four sides. This architecture offers the ultimate electrostatic control, paving the way for sub-3 nm scaling. Variations include Samsung’s Multi-Bridge Channel FET (MBCFET) and Intel’s RibbonFET.

Complementary Field-Effect Transistor (CFET)

Positioned as the successor to GAAFET for future sub-1 nm nodes (such as 7 Angstroms / A7), CFET vertically stacks n-type and p-type source-drain pairs on top of each other. This structural stacking reduces the transistor footprint by up to 50%, maximizing density.

Categorization of Semiconductor Nodes

Semiconductor production is broadly classified into three segments based on the node size and the complexity of the technology required.

Key Metrics Governing Node Advancements

The advancement from one semiconductor node to the next is evaluated using specific performance and structural indicators.

Moore’s Law

An empirical observation by Gordon Moore stating that the number of transistors on a microchip doubles approximately every two years, while the cost of computers is halved. While physical scaling has slowed, architectural innovations sustain its principles.

Dennard Scaling

The principle that as transistors get smaller, their power density stays constant, meaning power use is proportional to chip area. This law broke down in the mid-2000s due to sub-threshold leakage current, shifting industry focus toward multi-core architectures and energy efficiency rather than raw clock speed.

Transistor Density

Measured in Millions of Transistors per Square Millimeter (MTr/mm²). It serves as the true benchmark for comparing different manufacturers’ node capabilities, as a “7nm” node from one foundry may have a different density than a “7nm” node from another.

Lithography Techniques

The process of printing circuit patterns onto silicon wafers using light.

• Deep Ultraviolet (DUV): Uses argon fluoride (ArF) lasers at a 193 nm wavelength; utilized for mature and trailing-edge nodes.
• Extreme Ultraviolet (EUV): Uses light with a 13.5 nm wavelength; essential for patterning features below 7 nm.
• High-NA EUV: Next-generation EUV systems featuring a higher Numerical Aperture (0.55 NA compared to 0.33 NA), required for manufacturing sub-2 nm chips.

Global Semiconductor Foundry Landscape

The manufacturing of advanced semiconductor nodes is highly consolidated due to the immense capital expenditure required for fabrication facilities (Fabs) and lithography equipment.

• Taiwan Semiconductor Manufacturing Company (TSMC): The global leader in pure-play foundry market share, pioneering commercial production of 7nm, 5nm, and 3nm nodes.
• Samsung Electronics: The first foundry to implement GAAFET architecture commercially at its 3nm node.
• Intel Foundry: Progressing through its “5 nodes in 4 years” strategy, introducing PowerVia (backside power delivery) and RibbonFET at its Intel 20A and 18A (angstrom-era) nodes.

India’s Semiconductor Initiatives and Policy Landscape

India is actively building a domestic semiconductor ecosystem to reduce import dependencies and secure high-technology supply chains.

India Semiconductor Mission (ISM)

Launched under the Ministry of Electronics and Information Technology (MeitY) with an outlay of ₹76,000 crore. It provides financial support to companies investing in semiconductor fabrication, display fabs, and packaging units.

Modified Scheme for Setting Up Semiconductor Fabs

Offers a uniform fiscal support of 50% of the project cost for setting up semiconductor wafer fabrication facilities in India across all technology nodes (including mature and legacy nodes).

Key Domestic Projects

• Dholera Fab (Gujarat): India’s first commercial semiconductor fab, established by Tata Electronics in partnership with Taiwan’s Powerchip Semiconductor Manufacturing Corporation (PSMC), focusing on mature nodes (28nm) to supply automotive, power, and electronics sectors.
• Sanand ATMP Facility (Gujarat): An Assembly, Testing, Marking, and Packaging (ATMP) facility by Micron Technology to package memory chips.

Technical Trivia for UPSC Prelims

The Angstrom Era

As semiconductor nodes scale below 1 nm, the industry is transitioning units of measurement from nanometers (nm) to Angstroms (A), where 1 nm = 10 Angstroms. For example, a 2 nm node is equivalent to 20 Angstroms.

Silicon Limit

The theoretical physical limit where silicon can no longer function effectively as a semiconductor due to uncontrollable quantum tunneling effects when gates become only a few atoms wide. This has triggered research into 2D transitional metal dichalcogenides (TMDs) like MoS2 to replace silicon channels.

Backside Power Delivery Network (BSPDN)

A structural innovation that moves the power distribution wires from the top of the silicon die to the backside. This decouples the power network from the data signaling network, reducing voltage drop and saving routing space on advanced nodes.